In the effort to build integrated circuits with higher performance and increased yields a number of process technologies have emerged. One such technology improvement is the innovation of using a sacrificial gate to improve the geometry and manufacturability and performance of a gate structure. A second improvement in increasing integrated circuit performance involves processes that include an underlying strained semiconductor layer.
A typical process to form a device may consist of various steps. Known and related art may include the following steps. Using a starting wafer or substrate, a thin film layer of silicon dioxide is used to initially develop the silicon surface for processing. Next, masks, usually silicon nitride, are used to fabricate multiple layers. Chemical vapor deposition process or the equivalent may be used to define and form the active areas of the switching device, and wet etch stages may utilize phosphoric acid to subsequently remove unwanted depositions.
For MOS devices, a gate dielectric layer, and then a gate electrode are formed on a silicon base or substrate. First, the substrate surface is prepared for processing, and a well region is formed in the substrate. Next, a gate structure including a gate dielectric, sidewalls and sidewall spacers are formed. Later, implantation and oxide growth steps are generally used to develop the electrical characteristics of the various areas within a device. A source and drain region are usually formed by implantation or diffusion in the top surface of the silicon substrate after the gate formation. A sacrificial gate electrode may be removed in preparation for the deposition of the permanent gate electrode material. Further steps refining the geometry and electrical characteristics of the transistor may be performed as well as the later steps to open contact windows and the development of an interconnecting structure.
A drawback to forming a sacrificial gate structure is encountered in performing a metal polish process where a number of defects or a high defectivity rate may be introduced. Possible defects remain in and around the remaining gate structure and inter level dielectric layer.
With respect to performance enhancements of silicon switching devices, one of the recent innovations includes forming a strained substrate layer on an underlying substrate before forming any switching devices. Typically, a thin strained silicon layer is fabricated on a relaxed silicon germanium layer. MOS devices are then fabricated on the underlying strained silicon layer. The strained silicon layer is created by a crystalline mismatch by using a material, such as silicon germanium, with a lattice constant greater than or different than that of silicon. The lattice constant of germanium is about 4 percent greater than that of silicon. As a result, the silicon crystal is stressed when deposited on top of a substrate containing germanium. The crystalline mismatch results in the upper layers of silicon becoming strained, which creates increased hole and electron mobility within a formed silicon switch. Electrons passing through the stressed silicon experience an increased flow, which results in performance increases in the switching devices formed above the stressed silicon layers.
However, a difficulty with strained silicon technology is the presence of the relaxed silicon germanium layer under the strained silicon layer, where the silicon germanium layer may be affected by various processing steps, such as thermal oxidation, salicide formation, and anealling during an MOS device fabrication. Another problem when forming a strained silicon layer is a subsequent exposure to elevated temperatures during later processing steps may effectively remove some or all of the crystalline strain developed in the underlying silicon layer.